Base Relative Index Register Addressing Copy of a byte or word is transferred from the source register to the destination register i. Direct Addressing Moves a byte or word between a memory location directly i. The microprocessor first identifies the data location and then the data will be picked up and will be stored in the Dx register. The microprocessor will add 0H to this location [H] and makes the real location [H] Indirect Addressing Modes Register Indirect Addressing Transfer a byte or word between a register and memory location addressed by an index register or base register. The base register is base pointers and Bx. The example will be as follows.

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Unlike, , an microprocessor has bit address bus. Thus, is able to access i. As we know that a microprocessor performs arithmetic and logic operations. And an microprocessor is able to perform these operations with bit data in one cycle. Hence is a bit microprocessor. Thus the size of the data bus is bit as it can carry bit data at a time.

The architecture of microprocessor, is very much different from that of microprocessor. We have already discussed the introduction to the microprocessor and microprocessor. So, lets now proceed further and understand the architecture and working of microprocessor. The BIU functions in such a way that it: Fetches the sequenced instruction from the memory, Finds the physical address of that location in the memory where the instruction is stored and Manages the 6-byte pre-fetch queue where the pipelined instructions are stored.

An microprocessor exhibits a property of pipelining the instructions in a queue while performing decoding and execution of the previous instruction. This saves the processor time of operation by a large amount. This pipelining is done in a 6-byte queue. Also, the BIU contains 4 segment registers. Each segment register is of bit. The segments are present in the memory and these registers hold the address of all the segments. These registers are as follows: 1.

Code segment register: It is a bit register and holds the address of the instruction or program stored in the code segment of the memory. Also, the IP in the block diagram is the instruction pointer which is a default register that is used by the processor in order to get the desired instruction.

The IP contains the offset address of the next byte that is to be taken from the code segment. Stack segment register: The stack segment register provides the starting address of stack segment in the memory.

Data segment register: It holds the address of the data segment. The data segment stores the data in the memory whose address is present in this bit register. Extra segment register: Here the starting address of the extra segment is present. This register basically contains the address of the string data. It is to be noteworthy that the physical address of the instruction is achieved by combining the segment address with that of the offset address. As at the time of decoding and execution of the instruction in EU, the BIU fetches the sequential upcoming instructions and stores it in this queue.

The size of this queue is 6-byte. This means at maximum a 6-byte instruction can be stored in this queue. Execution Unit EU The Execution Unit EU performs the decoding and execution of the instructions that are being fetched from the desired memory location.

Control Unit: Like the timing and control unit in microprocessor, the control unit in microprocessor produces control signal after decoding the opcode to inform the general purpose register to release the value stored in it. And it also signals the ALU to perform the desired operation. ALU: The arithmetic and logic unit carries out the logical tasks according to the signal generated by the CU.

The result of the operation is stored in the desired register. Flag: Like in , here also the flag register holds the status of the result generated by the ALU. It has several flags that show the different conditions of the result. Operand: It is a temporary register and is used by the processor to hold the temporary values at the time of operation.

The reason behind two separate sections for BIU and EU in the architecture of is to perform fetching and decoding-executing simultaneously.

Now in this section, we will have a look at the overall processing cycle of microprocessor. So, basically, when an instruction is to be fetched from the memory, then firstly its physical address must be calculated and this is done at the BIU.

So, the generated physical address is H. Here, the code segment register provides the base address of the code segment which is combined with the offset address. The code segment contains the instructions.

Each time an instruction is fetched the offset address inside the code segment gets incremented. So, once the physical address of an instruction is calculated by the BIU of the processor, it sends the memory location by the address bus to the memory.

Further, the desired instruction at that memory location which is present in the form of the opcode is fetched by the microprocessor through the data bus. But, inside the memory, it will be in the form of an opcode. So, this opcode is sent to the control unit. The control unit decodes the opcode and generates control signals that inform the BL and CL register to release the value stored in it.

BL denotes the destination of the result of the add operation. This clearly shows that whatever, the operation is performed its result must be stored in the first register i. This means that the operand which is 05H is to be added with the data present in the CL register and is stored in that particular register i.

In such condition, the operand is not provided to the control unit as only the opcode is required to be decoded by the CU. Hence the operand is directly provided to the ALU. Also, the status of this result is stored in the flag register. So, whenever, ALU carries out an operation, it simultaneously generates the result as well as its status. It is to be noteworthy that in BIU, pipelining fails whenever there is branching in the instruction. This is because generally instructions are present in a sequential manner.

But, sometimes the instructions are required to be executed unsequentially. However, in the queue, the instructions are stored sequentially. So, in case there exist a need for any random instruction to be decoded. The opcode stored in the queue will become invalid and must be cleared at that particular time. So, this is all about the block diagram and working of microprocessor. You Might Also Like:.


Microprocessor - 8086 Functional Units

EU Execution Unit Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. EU has no direct connection with system buses as shown in the above figure, it performs operations over data through BIU. Let us now discuss the functional parts of microprocessors. Flag Register It is a bit register that behaves like a flip-flop, i.


Execution Unit (EU):

Unlike, , an microprocessor has bit address bus. Thus, is able to access i. As we know that a microprocessor performs arithmetic and logic operations. And an microprocessor is able to perform these operations with bit data in one cycle.


8086 Microprocessor




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